This Is Not Your Father’s Semiconductor Packaging: An EDA Perspective

The webinar held by John Park from Cadence Design Systems will take place on June 17th, 2020 from 12.00 p.m. to 12.45 p.m. (Eastern time).

Semiconductor foundries are accelerating their offerings for advanced packaging. This sea change in the advanced packaging market brings several important new solutions to the industry as well as significant design and analysis challenges for the packaging engineer. Many packaging professionals are becoming aware that the typical design flows used today for BGA packages have gaping holes when targeting the newer 2.5D-/3D-IC packaging technologies.  Get an overview of the trends and advancements for foundry-based 2.5D-IC, 3D-IC, and FOWLP solutions. Learn about the challenges  and benefits of the modernized design flow for foundry-based packaging.

John Park brings over 35 years of design and EDA experience to his role as Product Management Director for Advanced Semiconductor Packaging at Cadence Design Systems. In this role, John leads a team responsible for defining cross-domain solutions and methodologies for IC, package & PCB co-design and analysis.

This webinar will be hosted via Webex. Registrants will receive an email prior to the start of the webinar with login instructions. No participation fee is charged for students and IMAPS members. Non-members have to pay 50 $. You can register for the webinar here.